Arbetsbeskrivning

Our company is a consulting firm, and we are looking for a Senior Design-for-Test (DFT) Engineer to join our client’s team. The detailed job description for this role is provided below:

Location: Sweden (Remote/Hybrid Work Available)

Employment Type: Full-time

Job Description

As a Senior DFT Engineer, you will own the definition, insertion, verification, and validation of Design-for-Test architectures for complex SoCs and test chips. You will craft scan, LBIST/MBIST, boundary-scan, and compression solutions that maximize fault coverage while meeting aggressive power, performance, and area (PPA) targets. Working closely with RTL, physical design, and post-silicon teams, you will ensure every design is production-worthy and diagnosable from day one.

Key Responsibilities:

• Define DFT strategy, test access architecture, and coverage goals for new silicon projects.
• Insert and validate scan chains, EDT/compression logic, boundary-scan (1149.1/1149.6), and IEEE 1838/1500 wrappers.
• Develop and run ATPG, LBIST, and MBIST flows (Tessent, Modus, etc.) to achieve target coverage and pattern count.
• Implement and verify memory BIST with repair support (BISR), including BIRA controller and redundancy handling.
• Plan and integrate hierarchical or tile-based DFT structures including scan retargeting and wrapper chaining.
• Collaborate with physical design to optimize test routing, clocking, and DFT timing closure.
• Deliver ATE-ready pattern packages (STIL/WGL/eVCD) and support silicon debug, yield learning, and failure diagnosis.
• Develop IJTAG-based instrumentation access where applicable, and support bus-based test delivery if required.
• Automate DFT flows using Tcl, Python, or Perl; maintain regression infrastructure and debug tools.
• Contribute to design reviews, methodology improvements, and DFT IP road-mapping.

Required Qualifications:

• Master’s degree (or higher) in Electrical or Computer Engineering or related field.
• Minimum 5 years of hands-on experience in DFT ownership for complex ASICs or SoCs.
• Proficient in scan-based test, ATPG, LBIST, MBIST, and test compression architecture.
• Deep familiarity with EDA tools such as Tessent (Mentor/Siemens), Synopsys TetraMAX, or Cadence Modus.
• Experience with scripting languages like Tcl, Python, or Perl for flow automation.
• Strong understanding of STA constraints related to test clocks and compression logic.
• Practical experience with IEEE 1149.x, IEEE 1500, and optionally IEEE 1838 or 1687 (IJTAG).
• Exposure to DFT for tile-based or 3DIC designs, including inter-die boundary scan, packetized test delivery, and scan retargeting, is a strong plus.
• Excellent analytical, debugging, and communication skills in a cross-functional environment.

• Language Skills:

English: Fluent (Required)

Swedish & Chinese: Proficiency Highly Preferred, ensuring seamless coordination with both local clients and the headquarters.

Why Join Us

By joining our client’s team, you will become part of a highly experienced group of industry professionals where you can learn and apply the most advanced test methodologies in the field. The team is results-driven, highly flexible, and encourages innovation and ownership. In addition, the compensation package for this role is highly competitive within the Swedish market.