Arbetsbeskrivning

Our company is a consulting firm, and we are looking for a Senior Physical Design Engineer to join our client’s team. The detailed job description for this role is provided below:

Location: Sweden (Remote/Hybrid Work Available)

Employment Type: Full-time

Job Description

As a Senior Physical Design Engineer, you will drive block-level and full-chip implementation from RTL netlist through GDSII. You will deliver timing-clean, power-efficient, and DRC/LVS-clean layouts while collaborating with architecture, DFT, and packaging teams to meet tape-out schedules. Your work spans floorplanning, PnR, clock-tree synthesis, static timing analysis, IR/EM sign-off, and ECO closure.

Key Responsibilities:

• Own floorplanning including partitioning, pin placement, power planning, and macro integration.
• Drive complete place-and-route flow: placement, clock tree synthesis (CTS), optimization, and routing.
• Perform hierarchical STA (setup, hold, OCV, CPPR) and resolve timing violations through physical or logical ECOs.
• Analyze and fix congestion, IR-drop, EM, and physical signoff violations (DRC, LVS, ERC).
• Implement multi-voltage and low-power design techniques using UPF/CPF.
• Integrate DFT logic, scan chains, memory BIST, and compression logic into timing and physical flows.
• Deliver final GDSII, signoff reports, and manufacturing handoff packages.
• Automate physical design tasks using Tcl, Python, or Makefile-based flows.
• Collaborate with design, DFT, verification, and package teams to ensure first-pass success.

Required Qualifications:

• Master’s degree in Electrical or Computer Engineering or equivalent.
• Minimum 5 years of hands-on experience in block and top-level physical implementation.
• Strong expertise in physical design tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler.
• Solid understanding of static timing analysis using Tempus or PrimeTime.
• Hands-on experience with power grid design, IR/EM validation, signal integrity, and DRC/LVS closure.
• Familiarity with low-power design concepts: isolation cells, level shifters, power gating, multi-Vt domains.
• Experience implementing physical design in advanced FinFET nodes (e.g., 7nm, 5nm, 3nm), including awareness of double-patterning and EM/IR challenges.
• Proficiency in Tcl, Python, or Perl for automation and analysis.
• Excellent communication skills and cross-functional collaboration mindset.

Language Skills:

English: Fluent (Required)

Swedish & Chinese: Proficiency Highly Preferred, ensuring seamless coordination with both local clients and the headquarters.

Why Join Us

By joining our client’s team, you will become part of a highly experienced group of industry professionals where you can learn and apply the most advanced test methodologies in the field. The team is results-driven, highly flexible, and encourages innovation and ownership. In addition, the compensation package for this role is highly competitive within the Swedish market.