Arbetsbeskrivning

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.

Assignment Description:

We are looking for a Senior UVM Verification Engineer to join our dynamic team.

What you will work on:

• Develop and execute UVM-based testbenches for complex digital designs.
• Create and maintain verification plans, test cases, and coverage metrics.
• Collaborate with design engineers to interpret specifications and resolve issues.
• Analyze simulation results, document findings, and present them to design and verification teams.
• Drive continuous improvements in verification methodologies, tools, and workflows.

What you bring:

• Strong hands-on experience with UVM (Universal Verification Methodology).
• Proficiency in SystemVerilog and digital verification concepts.
• Practical experience with industry-standard simulation tools (Mentor, Cadence, Synopsys).
• Bachelor’s or Master’s degree in Electronics, Computer Engineering, or related field.
• Strong teamwork, problem-solving, and communication skills.

Nice to have:

• Experience with coverage-driven verification.
• Familiarity with Python, Perl, or TCL for scripting and automation.