Arbetsbeskrivning

We are looking for a skilled FPGA Developer with strong expertise in RTL design and verification, to join our growing team. You will work on high-performance digital designs targeting FPGA/ASIC platforms, with a primary focus on RTL design and verification in SystemVerilog or VHDL. The ideal candidate is not only technically strong but also a team player with excellent communication and collaboration skills, capable of working effectively in agile environments.

Key Responsibilities:

• RTL design and verification in SystemVerilog or VHDL
• Synthesis and implementation for FPGA or ASIC targets
• Design and development of reusable IP blocks
• Collaborate with verification and integration teams to ensure functional correctness and system integration
• Maintain high-quality design documentation and version control practices
• Fluency in both Swedish and English is required for this role.

Desirable Skills & Experience:

• Experience in any of the following areas will be considered a strong plus:
• UVM-based verification methodologies
• Top-level design integration
• Working in Agile environments with CI/CD pipelines
• Version control using Git
• Scripting knowledge in TCL, Python, Perl, Bash, or C-shell

This role is primarily focused on RTL design and verification, and we’re especially looking for someone who also has strong social and communication skills.

Location: Lund, Sweden