Arbetsbeskrivning

Role: ASIC Verification Engineer

Seniority Level: Senior

Location: Stockholm, Sweden (on-site only)

Remote Work: Not permitted (0%)

Application Deadline: 15 June 2025

Responsibilities

The consultant will be expected to:

• Define verification requirements and strategies for ASIC designs based on functional specifications.
• Follow the client's established development and verification methodologies.
• Develop and implement:
• Verification environments
• Test cases
• Verification plans
• Measure and analyze:
• Functional coverage
• Code coverage
• Debug RTL in close collaboration with ASIC designers.
• Interact with cross-functional teams to understand system-level requirements.
• Contribute to ongoing improvements in tools, processes, and verification flows.
• Produce and maintain clear, structured documentation.
• Mentor and support junior engineers.

Required Qualifications

• 5+ years of experience in ASIC verification.
• Master’s degree in Electrical Engineering, Computer Engineering, or related discipline.
• Strong expertise in:
• SystemVerilog
• UVM methodology
• Practical experience in Formal Verification.
• Additional knowledge (preferred, not mandatory):
• C programming
• Emulation environments
• High-Level Synthesis (HLS)
• Strong analytical and problem-solving skills.
• Ability to work independently and take initiative.
• Fluent in spoken and written English.
• Strong team player with good communication skills.